-- VHDL code position: p312_ex10_2_share_resource.txt -- Note : The code is about design optimize OF VHDL, -- -- -- See Also: example 10-1 -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY multmux IS PORT ( A0, B0, B : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); sel : IN STD_LOGIC; result : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ); END ENTITY multmux; ARCHITECTURE bhv OF multmux IS SIGNAL temp : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); BEGIN PROCESS ( A0, A1, B, sel ) BEGIN IF sel = '0' THEN temp <= A0 ; ELSE temp <= A1 ; END IF; result <= temp * B ; END PROCESS; END ARCHITECTURE bhv;