合肥工业大学：EDA技术与应用（精品课程）：p319_ex10_8_speed_optimize_pipeling_yes

-- VHDL code position: p319_ex10_8_speed_optimize_pipeling_yes.txt -- Note : The code is about speed optimize using pipeling design OF VHDL, -- -- -- See Also: example 10-7 -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY pipeadd IS PORT ( clk : IN STD_LOGIC; a0, a1, a2, a3 : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); yout : OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ) ); END ENTITY pipeadd; ARCHITECTURE pipelining_arch OF pipeadd IS SIGNAL t0, t1, t2, t3 : STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); SIGNAL addtmp0, addtmp1 : STD_LOGIC_VECTOR ( 8 DOWNTO 0 ); BEGIN PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk = '1' ) THEN t0 <= a0; t1 <= a1; t2 <= a2; t3 <= a3; END IF; END PROCESS; PROCESS ( clk ) BEGIN IF ( clk'EVENT AND clk = '1' ) THEN addtmp0 <= '0' & t0 + t1; addtmp1 <= '0' & t2 + t3; yout <= '0' & addtmp0 + addtmp1; END IF; END PROCESS; END ARCHITECTURE pipelining;