合肥工业大学：EDA技术与应用（精品课程）：p292_exer9_8_code_analyse

-- VHDL code position: p292_exer9_8_code_analyse.txt -- Note : Here have two VHDL codes, Please compare then, -- Talk out which is in reason. -- -- See Also: no -- Debug : no debug --------------------------------------------------------------------------------- -------------------------------------------------------------- -- code one -- -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk, a, b : IN STD_LOGIC; y : OUT STD_LOGIC ); END ENTITY EXAP; ARCHITECTURE bhv OF EXAP IS SIGNAL x : STD_LOGIC; BEGIN PROCESS BEGIN WAIT UNTIL clk = '1'; x <= '0'; y <= '0'; IF a <= b THEN x <= '1'; END IF; IF x <= '1' THEN y <= '1'; END IF; END PROCESS; END ARCHITECTURE bhv; -------------------------------------------------------------- -- code two -- -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY EXAP IS PORT ( clk, a, b : IN STD_LOGIC; y : OUT STD_LOGIC ); END ENTITY EXAP; ARCHITECTURE bhv OF EXAP IS BEGIN PROCESS VARIABLE x : STD_LOGIC; BEGIN WAIT UNTIL clk = '1'; x := '0'; y <= '0'; IF a <= b THEN x := '1'; END IF; IF x <= '1' THEN y <= '1'; END IF; END PROCESS; END ARCHITECTURE bhv;