合肥工业大学：EDA技术与应用（精品课程）：p280_ex9_20_concurrent_statement_BLOCK_gat

-- VHDL code position: p280_ex9_20_concurrent_statement_block_gat -- Note : This is code for explaing block statement -- in concurrent_statement of VHDL -- -- See Also: example 9_20, 9_21 -- Debug : no debug --------------------------------------------------------------------------------- -- kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- BLOCK Concurrent Statement Syntax: -- -- <Block Label> : -- BLOCK [ ( <Guard Expression> ) ] [ IS ] -- <Block Header> -- <Block Declarative Part> -- BEGIN -- <Block Statement Part> -- END BLOCK [ <Block Label> ] ; -- -- Notes: -- Guard Expression : 块保护表达式 -- Block Header : 接口语句 -- Block Declarative Part : 类属语句 -- Block Statement Part : 块并行语句 -- ENTITY gat IS GENERIC ( l_time : TIME; s_time : TIME }; PORT { b1, b2, b3 : INOUT BIT }; END ENTITY gat; ARCHITECTURE behav OF gat IS SIGNAL a1 : BIT; BEGIN blk1: BLOCK GENERIC ( gb1, gb2 : TIME ); GENERIC MAP ( gb1 => l_time, gb2 => s_time ); PORT ( pb : IN BIT; pb1 : INOUT BIT ); PORT MAP ( pb1 => b1; pb2 => a1 }; CONSTANT dela:Time= 1 ms; SIGNAL s1 : BIT; BEGIN s1 <= pb1 AFTER delay; pb2 <= s1 AFTER gb1, b1 AFTER gb2; END BLOCK blk1; END ARCHITECTURE behav;