-- VHDL code position: p271_ex9_13_sequence_statement_wait_until4 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9_9, 9_10, 9_11, 9_12, 9_13. -- Debug : no debug --------------------------------------------------------------------------------- -- 4 kinds of WAIT statement -- WAIT --- 1 WAIT ON singal list --- 2 WAIT UNTIL contidion expression --- 3 WAIT FOR time expression --- 4 -- 3 kinds of WAIT - UNTIL statement -- WAIT UNTIL signal = value WAIT UNTIL signal'EVENT AND signal = value WAIT UNTIL NOT clock'STABLE AND clock = '1'; -- 4 kind WAIT WAIT - UNTIL statement with same hardware circuit -- WAIT UNTIL clock = '1' WAIT UNTIL rising_edge ( clock ) WAIT UNTIL NOT clock'STABLE AND clock = '1'; WAIT UNTIL clock'EVENT AND clock = '1' ---------------------------------------------------------------- -- Fellowing is example code -- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY shifter IS PORT ( data : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); shift_left : IN STD_LOGIC; shift_right : IN STD_LOGIC; clk : IN BIT; reset : IN BIT; mode : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); qout : BUFFER STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) ); END ENTITY shifter; ARCHITECTURE bhv OF shifter IS SIGNAL enable : STD_LOGIC; BEGIN PROCESS BEGIN WAIT UNTIL ( rising_edge ( clk ) ); IF reset = '1') THEN qout <= "00000000"; ELSE CASE mode is WHEN "01" => qout <= shift_right & qout ( 7 DOWNTO 1 ); WHEN "10" => qout <= qout ( 6 DOWNTO 1 ) & shift_left ; WHEN "11" => qout <= data; WHEN OTHERS=> qout <= NULL ; END CASE; END IF; END PROCESS; END ARCHITECTURE bhv;