合肥工业大学：EDA技术与应用（精品课程）：p268_ex9_8_sequence_statement_exit

-- VHDL code position: p268_ex9_8_sequence_statement_exit -- Note : This is code for explaing sequence_statement of VHDL -- See Also: no -- Debug : no debug --------------------------------------------------------------------------------- SIGNAL a, b : STD_LOGIC_VECTOR ( 1 DOWMTO 0 ) SIGNAL a_less_then_b : BOOLEAN; ...... a_less_then_b <= FALSE; FOR i IN 1 DOWNTO 0 LOOP IF ( a( i ) = '1' AND b ( i ) = '0' ) THEN a_less_then_b <= FALSE; EXIT; ELSIF ( a( i ) = '0' AND b ( i ) = '1' ) THEN a_less_then_b <= TRUE; EXIT; ELSE null; END IF; END LOOP; ......