合肥工业大学：EDA技术与应用（精品课程）：p263_ex9_1_sequence_statement_mux41

-- VHDL code position: p263_ex9_41_sequence_statement_mux41 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-1, 9_2, 9_3, 9-4, 9_5, -- Debug : no debug --------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity mux4 is port ( s1, s2, s3, s4 : in std_logic; z1, z2, z3, z4 : out std_logic ); end mux4 ; architecture activ of mux4 is SIGNAL sel : INTEGER RANGE 0 TO 15; begin process( sel, s1, s2, s3, s4 ) begin sel <= '0'; if( s1 = '1' ) then sel <= sel +1; elsif ( s2 = '1' ) then sel <= sel + 1; -- 方向向左 end if; end process; end architecture activ ;