-- VHDL code position: p258_ex8_38_experiment8_3_ball -- Note : This is code file of tennis play -- See Also: example 8_35(top module), 8_36, 8_37, 8_38, 8_39, 8_40, 8_41, 8_42 -- Debug : no debug --------------------------------------------------------------------------------- -- 乒乓球灯模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ball is port ( clk : in std_logic; -- 乒乓球灯前进时钟 clr : in std_logic; -- 乒乓球灯清零 way : in std_logic; -- 乒乓球灯前进方向 en : in std_logic; -- 乒乓球灯使能 ballout : out std_logic_vector(7 downto 0) -- 乒乓球灯 ); end entity ball; architecture ful of ball is signal lamp : std_logic_vector(9 downto 0); begin process( clk, clr, en ) begin if( clr = '1' ) then -- 清零 lamp <= "1000000001"; elsif en = '0' then elsif ( clk'event and clk='1') then -- 使能允许，乒乓球灯前进时钟上升沿 if ( way='1' ) then -- 乒乓球灯右移 lamp( 9 downto 1 ) <= lamp( 8 downto 0 ); lamp( 0 ) <= '0'; else -- 乒乓球灯左移 lamp( 8 downto 0 ) <= lamp( 9 downto 1 ); lamp( 9 ) <= '0'; end if; end if; ballout <= lamp( 8 downto 1 ); end process; end architecture ful;