-- VHDL code position: p260_ex8_41_experiment8_3_cou4 -- Note : This is code file of tennis play -- See Also: example 8_35(top module), 8_36, 8_37, 8_38, 8_39, 8_40, 8_41, 8_42 -- Debug : no debug --------------------------------------------------------------------------------- -- 四进制计数器用来做失球高位计数 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cou4 is port ( clk, clr : in std_logic; cout : out std_logic; qout : out std_logic_vector( 3 downto 0 ) ); end entity cou4; architecture ful of cou4 is signal qqout : std_logic_vector(3 downto 0); begin process( clr, clk ) begin if( clr = '1' ) then qqout <= "0000"; cout <= '0'; elsif( clk'event and clk = '1' ) then if( qqout > "0010" )THEN qqout <= "0000"; cout <= '1'; else qqout <= qqout + '1'; cout <= '0'; end if; end if; qout <= qqout; end process; end architecture ful ;