合肥工业大学：EDA技术与应用（精品课程）：p267_ex9_5_sequence_statement_loop

-- VHDL code position: p267_ex9_5_sequence_statement_loop -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-4, 9_5, -- Debug : no debug --------------------------------------------------------------------------------- SIGNAL a, b, c : STD_LOGIC_VECTOR ( 1 TO 3 ); ...... FOR n IN 1 TO 3 LOOP a <= b(n) AND c(n); END LOOP; .... -- above loop statement can be replaced fellowing a( 1 ) <= b( 1 ) AND c( 1 ); a( 2 ) <= b( 2 ) AND c( 2 ); a( 3 ) <= b( 3 ) AND c( 3 );