合肥工业大学：EDA技术与应用（精品课程）：p270_ex9_12_sequence_statement_wait_UNTIL3.TXT

-- VHDL code position: p270_ex9_11_sequence_statement_wait_until2 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9_9, 9_10, 9_11, 9_12, 9_13. -- Debug : no debug --------------------------------------------------------------------------------- -- 4 kinds of WAIT statement -- WAIT --- 1 WAIT ON singal list --- 2 WAIT UNTIL contidion expression --- 3 WAIT FOR time expression --- 4 -- 3 kinds of WAIT - UNTIL statement -- WAIT UNTIL signal = value WAIT UNTIL signal'EVENT AND signal = value WAIT UNTIL NOT clock'STABLE AND clock = '1'; -- 4 kind WAIT WAIT - UNTIL statement with same hardware circuit -- WAIT UNTIL clock = '1' WAIT UNTIL rising_edge ( clock ) WAIT UNTIL NOT clock'STABLE AND clock = '1'; WAIT UNTIL clock'EVENT AND clock = '1' --- Fellowing is 1 example about WAIT-UNTIL statement PROCESS BEGIN WAIT UNTIL clk = '1'; avr <= a; WAIT UNTIL clk = '1'; avr <= avr + a; WAIT UNTIL clk = '1'; avr <= avr + a; WAIT UNTIL clk = '1'; avr <= ( avr + a ) / 4; END PROCESS;