-- VHDL code position: p273_ex9_14_sequence_statement_PROCEDURE -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9_14, 9_15. -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE data_types IS SUBTYPE data_element IS INTEGER RANGE 0 TO 3 TYPE data_array IS ARRAY (1 TO 3 ) of data_element; END PACKAGE data_types USE WORK.data_type.ALL; ENTITY sort IS PORT ( in_array : IN data_array; out_array : OUT data_array ); END ENTITY sort; ARCHITECTURE bhv OF sort IS SIGNAL enable : STD_LOGIC; BEGIN PROCESS ( in_array ) PROCEDURE swap ( data : INOUT data_array; low, high : IN INTEGER ) IS VARIABLE temp : data_element; BEGIN IF ( data ( low ) > data ( high ) ) THEN temp := data ( low ); data( low ) := data ( high ); data( high ):= temp; END IF; END PROCEDURE swap; VARIABLE my_array : data_array; BEGIN my_array := in_array; swap (my_array, 1, 2 ); swap (my_array, 2, 3 ); swap (my_array, 1, 2 ); out_array <= my_array; END PROCESS; END ARCHITECTURE bhv; --- Fellowing is 1 example about WAIT-UNTIL statement PROCESS BEGIN rst_loop: LOOP WAIT UNTIL clock = '1' AND clock'EVENT; NEXT rst_loop WHEN ( rst = '1'); x <= a; WAIT UNTIL clock = '1' AND clock'EVENT; NEXT rst_loop WHEN ( rst = '1'); x <= b; END LOOP rst_loop; END PROCESS;