-- VHDL code position: p273_ex9_15_sequence_statement_PROCEDURE_sort4 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9_14, 9_15. -- Debug : no debug --------------------------------------------------------------------------------- ENTITY sort4 IS GENERIC ( top : INTEGER := 3 ); PORT ( a, b, c, d : IN BIT_VECTOR ( 0 TO top ); ra, rb, rc, rd : OUT BIT_VECTOR ( 0 TO top ) ); END ENTITY sort4; ARCHITECTURE muxes OF sort4 IS PROCEDURE sort2 ( x, y : INOUT BIT_VECTOR ( 0 TO top ) ) IS VARIABLE temp : data_element; BEGIN IF x > y THEN tmp := x; x := y; y := tmp; END IF; END PROCEDURE sort2 BEGIN PROCESS ( a, b, c, d ) VARIABLE va, vb, vc, vd : BIT_VECTOR ( 0 TO top ); BEGIN va := a; vb := b; vc := c; vd := d; sort2 ( va, vc ); sort2 ( vb, vd ); sort2 ( va, vb ); sort2 ( vc, vd ); sort2 ( vd, vc ); ra <= va; rb <= vb; rc <= vc; rd <= vd; END PROCESS; END ARCHITECTURE muxes;