合肥工业大学：EDA技术与应用（精品课程）：p277_ex9_18_concurrent_statement_assigment_mux

-- VHDL code position: p277_ex9_18_concurrent_statement_assigment_mux -- Note : This is code for explaing assigment statement -- in concurrent_statement of VHDL -- -- See Also: example 9_18, 9_19 -- Debug : no debug --------------------------------------------------------------------------------- -- 7 kinds of concurrent statement: -- 1) Concurrent Signal Assigment -- 2) Proces Statement -- 3) Block Statement -- 4) Select Signal Assigment Statement -- 5) Component Instantiations Statement -- 6) Generate Statement -- 7) Concurrent Procedure Calls Statement -- Concurrent Statement Syntax: -- ARCHITECTURE name OF entity name IS -- -- Declare Statement -- -- BEGIN -- -- Concurrent Statement -- -- -- END ARCHITECTURE name ; ENTITY mux IS PORT { a, b : IN BIT; p1, p2 : IN BIT; z : OUT BIT ); END; ARCHITECTURE behav OF mux IS BEGIN z <= a WHEN p1 = '1' ELSE b WHEN p2 = '1' ELSE c; END;