VHDL code position: p174_ex7_1_s_machine Note: 1: the code is state machine code 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY s_machine IS PORT ( clk, reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR(0 DOWNTO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 ); END ENTITY s_machine; ARCHITECTURE BEHAV OF s_machine IS TYPE FSM_ST IS ( s0, s1, s2, s3 ); SIGNAL current_state, next_state: FSM_ST; BEGIN REG: PROCESS ( reset, clk ) IF reset = '1' THEN current_state <= s0; ELSIF clk = '1' AND clk'EVENT THEN current <= next_state; END IF; END PROCESS; COM: PROCESS ( current_state, state_inputs ) BEGIN CASE current_state IS WHEN s0 => comb_outputs <= 5; IF state_inputs = "00" THEN next_state <= s0; ELSE next_state <= s1; END IF; WHEN s1 => comb_outputs <= 8; IF state_inputs = "00" THEN next_state <= s1; ELSE next_state <= s2; END IF; WHEN s2 => comb_outputs <= 12; IF state_inputs = "11" THEN next_state <= s0; ELSE next_state <= s3; END IF; WHEN s3 => comb_outputs <= 14; IF state_inputs = "11" THEN next_state <= s3; ELSE next_state <= s0; END IF; END CASE; END PROCESS; END ARCHITECTURE BEHAV;