VHDL code position: p134_ex5_19_coder Note: 1: the code is explain condition judge of "if" statement 2: see also example 5_18 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY coder IS PORT ( din : IN STD_LOGIC_VECTOR(0 TO 7); output : OUT STD_LOGIC_VECTOR(0 TO 2) ); END ENTITY coder; ARCHITECTURE BEHAV OF coder IS SIGNAL SINT : STD_LOGIC_VECTOR( 4 DOWNTO 0 ) BEGIN PROCESS ( din ) BEGIN IF ( din( 7 ) ='0' ) THEN output <= "000"; -- din: "0XXXXXXX" (d7,d6,....d0) ELSIF ( din( 6 ) ='0' ) THEN output <= "100"; -- din: "10XXXXXX" (d7,d6,....d0) ELSIF ( din( 5 ) ='0' ) THEN output <= "010"; -- din: "110XXXXX" (d7,d6,....d0) ELSIF ( din( 6 ) ='0' ) THEN output <= "110"; -- din: "1110XXXX" (d7,d6,....d0) ELSIF ( din( 3 ) ='0' ) THEN output <= "001"; -- din: "11110XXX" (d7,d6,....d0) ELSIF ( din( 2 ) ='0' ) THEN output <= "101"; -- din: "111110XX" (d7,d6,....d0) ELSIF ( din( 1 ) ='0' ) THEN output <= "011"; -- din: "1111110X" (d7,d6,....d0) ELSE output <= "111"; -- din: "11111110" (d7,d6,....d0) END IF; END PROCESS; END ARCHITECTURE BEHAV;