VHDL code position: p148_ex5_24_FTCTRL Note: 1: the code is 8 bit frequency meter 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL IS PORT ( CLKK : IN STD_LOGIC; CNT_EN : OUT STD_LOGIC; RST_CNT : OUT STD_LOGIC; LOAD : OUT STD_LOGIC ); END ENTITY FTCTRL; ARCHITECTURE BEHAV OF FTCTRL IS SGINAL DIV2CLK : STD_LOGIC; BEGIN DIV2CLK_P: PROCESS ( CLKK ) BEGIN IF CLKK'EVENT AND CLKK = '1' THEN DIV2CLK<=NOT DIV2CLK; END IF; END PROCESS DIV2CLK_P; CLR_P: PROCESS (CLKK, DIV2CLK) BEGIN: IF CLKK ='0' AND DIV2CLK = '0' THEN RST_CNT <= '1'; ELSE RST_CNT <= '0'; END IF; END PROCESS; ` LOAD <= NOT DIV2CLK; CNT_EN <= DIV2CLK; END ARCHITECTURE BEHAV;