VHDL code position: p149_ex5_25_REG32B Note: 1: the code is 32 bit register 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY REG32B IS PORT ( LK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END ENTITY REG32B; ARCHITECTURE BEHAV OF REG32B IS BEGIN REG32B_P: PROCESS ( LK, DIN ) BEGIN IF LK'EVENT AND LK = '1' THEN DOUT <= DIN; END IF; END PROCESS REG32B_P; END ARCHITECTURE BEHAV;