VHDL code position: p131_ex5_17_tristate3 Note: 1: the code is 4 channel tri-state bus driver 2: this is correct code, compare with example 5_16 !!! ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY tristate3 IS PORT ( input0, input1, input2, input3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY tristate3; ARCHITECTURE BEHAV OF tristate3 IS BEGIN PROCESS ( enable, input0, input1, input2, input3 ) BEGIN output <= input3 WHEN enable = "00" ELSE ( OTHERS => 'Z' ); output <= input2 WHEN enable = "01" ELSE ( OTHERS => 'Z' ); output <= input1 WHEN enable = "10" ELSE ( OTHERS => 'Z' ); output <= input0 WHEN enable = "11" ELSE ( OTHERS => 'Z' ); END PROCESS; END ARCHITECTURE BEHAV;