VHDL code position: p146_ex5_23_pulse Note: 1: the code is frequency diviser accroding input digit 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY pulse IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); FOUT : OUT STD_LOGIC ); END ENTITY pulse; ARCHITECTURE BEHAV OF pulse IS SGINAL FULL : STD_LOGIC; BEGIN P_REG: PROCESS ( CLK ) VARIABLE CNT8: STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) BEGIN IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = "11111111" THEN CNT8 := D; FULL <= '1'; ELSE CNT8 := CNT8 + 1; FULL <= '0'; END IF; END IF; END PROCESS P_REG; P_DIV: PROCESS ( FULL ) VARIABLE CNT2: STD__LOGIC; BEGIN: IF FULL'EVENT AND FULL = '1' THEN CNT2 := NOT CNT2; IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF; END PROCESS P_DIV; ` END ARCHITECTURE BEHAV;