VHDL code position: p150_ex5_27_FREQTEST Note: 1: the code is top file of frequency meter 2: it's sub module file is example 5_24, 5_25, 5_26 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FREQTEST IS PORT ( CLK1HZ : IN STD_LOGIC; -- 1 HZ clk input FSIN : IN STD_LOGIC; -- frequency signal input ready for testing DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- test result output ); END ENTITY FREQTEST; ARCHITECTURE BEHAV OF FREQTEST IS COMPONENT FTCTRL PORT ( CLKK : IN STD_LOGIC; CNT_EN : OUT STD_LOGIC; RST_CNT : OUT STD_LOGIC; LOAD : OUT STD_LOGIC ); END COMPONENT; COMPONENT COUNTER32B PORT ( FIN : IN STD_LOGIC; -- frequnce input CLR : IN STD_LOGIC; -- clear signal ENABL : IN STD_LOGIC; -- enable counting DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- count output ); END COMPONENT; COMPONENT REG32B PORT ( LK : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; SIGNAL TSTEN1 : STD_LOGIC; SIGNAL CLR_CNT1 : STD_LOGIC; SIGNAL LOAD11 : STD_LOGIC; SIGNAL DTO1 : STD_LOGIC_VECTOR ( 31 DOWNTO 0 ); SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR ( 6 DOWNTO 0 ); BEGIN U1 : FTCTRL PORT MAP ( CLKK => CLK1HZ, CNT_EN => TSTEN1, RST_CNT => CLR_CNT1, LOAD => LOAD1 ) U2 : REG32B PORT MAP ( LK => LOAD1, DIN => DTO1, DOUT => DOUT ); U3 : COUNTER32B PORT MAP ( FIN => FSIN, CLR => CLR_CNT1, ENABL => TSTEN1, DOUT => DTO1 ); END ARCHITECTURE BEHAV;