VHDL code position: p138_ex5_20_mul Note: 1: the code is explain parallel statement by process 2: ------------------------------------------------------------------------------- LIBARY IEEE; -- USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mul IS PORT ( a, b, selx, sely : IN BIT; data_out : OUT BIT ); END ENTITY mul; ARCHITECTURE BEHAV OF mul IS SIGNAL temp : BIT BEGIN p_a: PROCESS ( a, b, selx ) BEGIN IF ( selx ='0' ) THEN temp <= a; ELSE temp <= b; END IF; END PROCESS p_a; p_b: PROCESS ( temp, c, sely ) BEGIN IF ( sely ='0' ) THEN data_out<= temp; ELSE data_out<= c; END IF; END PROCESS p_b; END ARCHITECTURE BEHAV;