VHDL code position: p149_ex5_26_COUNTER32B Note: 1: the code is 32 bit register 2: ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B IS PORT ( FIN : IN STD_LOGIC; -- frequnce input CLR : IN STD_LOGIC; -- clear signal ENABL : IN STD_LOGIC; -- enable counting DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- count output ); END ENTITY COUNTER32B; ARCHITECTURE BEHAV OF COUNTER32B IS SIGNAL CQI: ATD_LOGIC_VECTOR ( 31 DOWNTO 0 ); BEGIN COUNT_P: PROCESS ( FIN, CLR, ENABL ) BEGIN IF CLR = '1' THEN CQI <= ( OTHERS => '0' ); ELSIF FIN'EVENT AND FIN = '1' THEN IF ENABL = '1' THEN CQI <= CQI +1; END IF; END IF; END PROCESS COUNT_P; DOUT <= CQI; END ARCHITECTURE BEHAV;