VHDL code position: p188_ex7_8_ADC0809 Note: 1: The code is about state coding of FSM 2: Compare it with example 7_7 ------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -- USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADC0809 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK, EOC : IN STD_LOGIC; ALE, START, OE, ADDA, : OUT STD_LOGIC; c_state : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY ADC0809; ARCHITECTURE BEHAV OF ADC0809 IS TYPE states IS ( st0, st1, st2, st3, st4 ); SIGNAL current_state, next_state : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); CONSTANT st0 : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) := "000"; CONSTANT st1 : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) := "001"; CONSTANT st2 : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) := "010"; CONSTANT st3 : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) := "011"; CONSTANT st4 : STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) := "100"; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK : STD_LOGIC; BEGIN ADDA <= '1'; -- ADC0809 channel select: -- 0-channel 0; 1-channel 1 Q <= REGL; START <= current_state (4 ); -- ?? ALE <= current_state (3 ); -- ?? OE <= current_state (2 ); -- ?? LOCK <= current_state (1 ); -- ?? c_state <= current_state ; COM: PROCESS ( current_state, EOC ) BEGIN CASE current_state IS WHEN st0 => -- ADC 0809 initial next_state <= st1; WHEN st1 => -- ADC 0809 start sampling next_state <= st2; WHEN st2 => -- ADC 0809 state test and wait IF EOC = '1' THEN next_state <= st3; ELSE next_state <= st2; END IF; WHEN st3 => -- ADC 0809 data output next_state <= st4; WHEN st4 => next_state <= st0; WHEN OTHERS => next_state <=st0; END CASE; END PROCESS COM; REG: PROCESS ( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN current_state <= next_state; END IF; END PROCESS REG; LATCH1: PROCESS ( LOCK ) -- latch data in the rising edge of LOCK BEGIN IF LOCK'EVENT AND LOCK = '1' THEN REGL <= D; END IF; END PROCESS LATCH1; END ARCHITECTURE BEHAV;