合肥工业大学：EDA技术与应用（精品课程）：p198_ex7_13_SINDATA.TXT

VHDL code position: p198_ex7_13_sindata Note: 1: The code is LPM_ROM code, 2: It be created by File -> MegaWizard Plug-In Manager of MAX+PLUS II ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sindata IS PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END sindata; ARCHITECTURE SYN OF sindata IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_rom GENERIC ( lpm_width : NATURAL; lpm_widthad : NATURAL; lpm_address_control : STRING; lpm_outdata : STRING; lpm_file : STRING ); PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); lpm_rom_component : lpm_rom GENERIC MAP ( LPM_WIDTH => 8, LPM_WIDTHAD => 6, LPM_ADDRESS_CONTROL => "REGISTERED", LPM_OUTDATA => "UNREGISTERED", LPM_FILE => "./p196_ex7_12_sindata.mif" ) PORT MAP ( address => address, inclock => inclock, q => sub_wire0 ); END SYN;