-- VHDL code position: p212_ex8_1_andn -- Note: 1: This is code for explaining "GENERIC" statement -- 2: It's top design file see example 8_2 --------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; --USE ieee.std_logic_unsigned.all; ENTITY andn IS GENERIC ( n : INTEGER ); PORT ( a : IN STD_LOGIC_VECTOR( n-1 DWONTO 0 ); c : OUT STD_LOGIC ); END andn; ARCHITECTURE behav OF andn IS BEGIN PROCESS ( a ) VARIABLE int : STD_LOGIC ; BEGIN int := '1'; FOR i IN a'LENGTH -1 DOWNTO 0 LOOP IF a ( i )= '0' THEN int := '0'; END IF; END LOOP; c <= int ; END PROCESS; END ARCHITECTURE behav;