-- VHDL code position: p220_ex8_7_overload_operator -- Note : This is code for explaining "OVERLOADED OPERATOR" of VHDL -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; PACKAGE STD_LOGIC_UNSIGNED IS FUNCTION "+" ( L : STD_LOGIC_VECTOR; R : INTEGER ) RETURN STD_LOGIC_VECTOR; FUNCTION "+" ( L : INTEGER; R : STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION "+" ( L : STD_LOGIC_VECTOR; R : STD_LOGIC ) RETURN STD_LOGIC_VECTOR; FUNCTION SHR ( ARG : STD_LOGIC_VECTOR; COUNT : ST_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; END STD_LOGIC_UNSIGNED ; LIBRARY ieee; -- the statement is unwanted !!! USE ieee.std_logic_1164.all; -- the statement is unwanted !!! USE ieee.std_logic_arith.all; -- the statement is unwanted !!! PACKAGE BODY STD_LOGIC_UNSIGNED IS FUNCTION maximum ( L, R : INTEGER ) -- the function is unwanted !!! RETURN INTEGER IS -- the function is unrelate with overload operator !! BEGIN IF L > R THEN RETURN L; ELSE RETURN R; END IF; END FUNCTION maxumun; FUNCTION "+" ( L : STD_LOGIC_VECTOR; R : INTEGER ) RETURN STD_LOGIC_VECTOR IS VARIABLE result STD_LOGIC_VECTOR ( L'range ); BEGIN result := UNSIGNED(L) +R; RETURN STD_LOGIC_VECTOR ( result ); END FUNCTION "+"; ..... END PACKAGE BODY STD_LOGIC_UNSIGNED; FUNCTION "+" ( a, b : IN BIT_VECTOR ) RETURN BIT_VECTOR IS BEGIN IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; FUNCTION max ( a, b : IN INTEGER ) RETURN INTEGER IS BEGIN IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; END BODY packexp ; ------------------------------------------------------------------- -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE WORK.packexp.all; ENTITY axamp IS PORT ( a1, b1 : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); a2, b2 : IN BIT_VECTOR ( 4 DOWNTO 0 ); a1, b1 : IN INTEGER RANGE 0 TO 15; c1 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); c2 : OUT BIT_VECTOR ( 4 DOWNTO 0 ); c3 : OUT INTEGER RANGE 0 TO 15 ); END axamp; ARCHITECTURE behav OF axamp IS BEGIN out1 <= max (dat1, dat2); PROCESS ( dat2, dat4 ) BEGIN c1 <= max ( a1, b1 ); c2 <= max ( a2, b2 ); c3 <= max ( a3, b3 ); END PROCESS; END ARCHITECTURE behav;