-- VHDL code position: p212_ex8_2_exn -- Note: 1: This is code for explaining "GENERIC" statement -- 2: The code is top design code -- 3: It's sub design file see example 8_1 --------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; --USE ieee.std_logic_unsigned.all; ENTITY exn IS PORT ( d1, d2, d3, d4, d5, d6, d7 : IN STD_LOGIC; q1, q2 : OUT STD_LOGIC ); END exn; ARCHITECTURE behav OF exn IS COMPONENT andn GENERIC ( n : INTEGER ); PORT ( a : IN STD_LOGIC_VECTOR( n-1 DWONTO 0 ); c : OUT STD_LOGIC ); END COMPONENT; BEGIN u1: andn GENERIC MAP ( n >= 2 ); PORT MAP (a(0) >= d1, a(1) >= d2, c >= q1 ); u2: andn GENERIC MAP ( n >= 5 ); PORT MAP (a(0) >= d3, a(1) >= d4, a(2) >= d5, a(3) >= d6, a(4) >= d7, c >= q2 ); END ARCHITECTURE behav;