VHDL code position: p199_ex7_14_sindata Note: 1: The code is top design file for sin wave generate 2: sub-module see: example 7_13, 7_12 ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ENTITY SINGT IS PORT ( CLK : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END SINGT; ARCHITECTURE DACC OF SINGT IS COMPONENT SINADATA PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); SIGNAL Q1 : STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN PROCESS ( CLK ) BEGIN IF CLK'EVENT AND CLK = '1' THEN Q1 <= Q1+1;; END IF; END PROCESS; U1: SINDATA PORT MAP ( adress => Q1, => DOUT, inclock => CLK ); END ARCHITECTURE DACC;