合肥工业大学：EDA技术与应用（精品课程）：p190_ex7_9_case_others

VHDL code position: p190_ex7_9_case_others Note: 1: The code is explain "CASE -OTHERS" statement 2: ------------------------------------------------------------------------------- ............... TYPE states IS ( st0, st1, st2, st3, st4, st_ilg1, st_ilg2, st_ilg3 ); SIGNAL current_state, next_state : states; COM: PROCESS ( current_state, state_inputs ) BEGIN CASE current_state IS WHEN st0 => ....... WHEN st1 => ...... WHEN OTHERS => next_state <=st0; END CASE; END PROCESS COM; ................