VHDL code position: p210_ex7_19_DAC Note: 1: This is ADC implement code by DAC and compare 2: ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY DAC IS PORT ( CLK : IN STD_LOGIC; LM311 : IN STD_LOGIC; CLR : IN STD_LOGIC; DD : OUT STD_LOGIC_VECTOR( 7 DWONTO 0 ); DISPDATA : OUT STD_LOGIC_VECTOR( 7 DWONTO 0 ) ); END CNT9B; ARCHITECTURE behav OF DAC IS SIGNAL CQI : OUT STD_LOGIC_VECTOR( 7 DWONTO 0 ); BEGIN DD <= CQI; PROCESS ( CLK, CLR, LM311 ) BEGIN IF CLR = '1' THEN CQI <= "00000000"; ELSIF CLK'EVENT AND CLK = '1' THEN IF LM311 = '1' THEN CQI <= CQI + 1; END IF; END IF; END PROCESS; -- ADC output data , DISPDATA <= CQI WHEN LM311 = '0' ELSE "00000000"; END ARCHITECTURE behav;