合肥工业大学：EDA技术与应用（精品课程）：p222_ex8_9_procedure_comp

-- VHDL code position: p222_ex8_9_procedure_comp -- Note : This is code for explaining " PROCEDURE " of VHDL -- Debug : no debug --------------------------------------------------------------------------------- -- fellowing code have two errors, please correct the two errors !!! -- PROCEDURE comp ( a, r : IN REAL; m : IN INTEGER; v1, v2 : OUT REAL ) IS BEGIN v1 := 1.6 *a; v2 := 1.0; Q1: FOR cnt IN 1 TO m LOOP v2 := v2 * v1; EXIT Q1 WHEN v2 > v1; END LOOP Q1; ASSERT ( v2 < v1 ) REPORT "OUT OF REANE " SEVERITY ERROR; END PROCEDURE comp ;