合肥工业大学：EDA技术与应用（精品课程）：p236_ex8_14_DataTypeConvert_decoder3to8

-- VHDL code position: p236_ex8_14_DataTypeConvert_decoder3to8 -- Note : This is code for explaining different data type convert of VHDL -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY decoder3to8 IS PORT ( input : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0 ); output : OUT STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) ); END ENTITY decoder3to8; ARCHITECTURE behav OF decoder3to8 IS BEGIN PROCESS ( input ) BEGIN output <= (OTHERS => '0' ); output ( CONV_INEGER ( input ) ) <='1'; END PROCESS; END ARCHITECTURE behav;