合肥工业大学：EDA技术与应用（精品课程）：p239_ex8_16_operator_logic

-- VHDL code position: p239_ex8_16_operator_logic -- Note : This is code for explaining the use of logic operator of VHDL -- Debug : no debug --------------------------------------------------------------------------------- SIGNAL a, b, c : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); SIGNAL d, f, f, g : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ); SIGNAL h, i, j, k : STD_LOGIC; SIGNAL l, m, n, o, p: BOOLEAN; ...... a <= b AND c; d <= e OR f OR g; h <= ( i NAND j ) NAND k; l <= ( m XOR n ) AND k; l <= ( m XOR n ) OR k; a <= b AND e; h <= i OR l; ......