-- VHDL code position: p241_ex8_21_operator_get_sum3
-- Note : This is code for explaining the use of geting sum operator of VHDL
-- Debug : no debug
---------------------------------------------------------------------------------
PACKAGE example_arithmetic IS
TYPE small_INT IS RANGE 0 TO 7;
END example_arithmetic;
USE WORK.exmple_arithmetic.ALL;
ENTITY arithmetic IS
PORT ( a, b : IN SMALL_INT ;
m : OUT SMALL_INT
);
END ENTITY arithmetic;
ARCHITECTURE bhv OF arithmetic IS
BEGIN
c <= a + b ;
END ARCHITECTURE bhv;