合肥工业大学：EDA技术与应用（精品课程）：p246_ex8_26_experiment8_1_ANDARITH.TXT

-- VHDL code position: p246_ex8_26_experiment8_1_ANDARITH -- Note : This is code of multiplication by shifting -- See Also: example 8_24,8_25,8_26,8_27,8_28,8_29(top module) -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ANDARITH IS -- 选通与门模块 PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ANDARITH; ARCHITECTURE behav OF ANDARITH IS BEGIN PROCESS(ABIN, DIN) BEGIN FOR I IN 0 TO 7 LOOP -- 循环，完成8位与1位运算 DOUT(I) <= DIN(I) AND ABIN; END LOOP; END PROCESS; END behav;