-- VHDL code position: p248_ex8_29_experiment8_1_MULTI8X8 -- Note : This is code of multiplication by shifting -- See Also: example 8_24,8_25,8_26,8_27,8_28,8_29(top module) -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY MULTI8X8 IS -- 8位乘法器顶层设计 PORT ( clkk, hkey, START : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); ARIEND : OUT STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END MULTI8X8; ARCHITECTURE struc OF MULTI8X8 IS COMPONENT ARICTL PORT ( CLK, START : IN STD_LOGIC; CLKOUT, RSTALL, ARIEND : OUT STD_LOGIC ); END COMPONENT; COMPONENT ANDARITH PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); DOUT : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END COMPONENT; COMPONENT ADDER8B PORT ( CIN : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); S : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); COUT : OUT STD_LOGIC ); END COMPONENT; COMPONENT SREG8B PORT ( CLK, LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); QB : OUT STD_LOGIC ); END COMPONENT; COMPONENT REG16B PORT ( CLK, CLR : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR( 8 DOWNTO 0 ); Q : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ) ); END COMPONENT; SIGNAL GNDINT, INTCLK, RSTALL, NEWSTART, QB : STD_LOGIC; SIGNAL ANDSD : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL DTBIN : STD_LOGIC_VECTOR( 8 DOWNTO 0 ); SIGNAL DTBOUT : STD_LOGIC_VECTOR( 15 DOWNTO 0 ); BEGIN DOUT <= DTBOUT; GNDINT <= '0'; PROCESS( CLK, START ) BEGIN IF START='1' THEN NEWSTART <= '1'; ELSIF CLK='0' THEN NEWSTART <= '0'; END IF; END PROCESS; PROCESS ( hkey ) BEGIN IF ( hkey'EVENT AND hkey = '1' ) THEN axx <= maxx + '1' ; END IF; END PROCESS; PROCESS( clkk ) BEGIN IF clkk'EVENT AND clkk = '1' THEN IF ( count < maxx ) THEN count <= count + '1'; ELSE count <= "0000"; clk <= NOT clk; END IF; END IF; END PROCESS; U1 : ARICTL PORT MAP ( CLK => CLKK, START => NEWSTART, CLKOUT => INTCLK, RSTALL => RSTALL, ARIEND => ARIEND ); U2 : SREG8B PORT MAP ( CLK => INTCLK, LOAD => RSTALL, DIN => B, QB => QB ); U3 : ANDARITH PORT MAP ( ABIN => QB, DIN => A, DOUT => ANDSD ); U4 : ADDER8B PORT MAP ( CIN => GNDINT, A => DTBOUT(15 DOWNTO 8), B => ANDSD, S => DTBIN(7 DOWNTO 0), COUT => DTBIN(8) ); U5 : REG16B PORT MAP ( CLK => INTCLK, CLR => RSTALL, D => DTBIN, Q => DTBOUT ); END struc;