合肥工业大学：EDA技术与应用（精品课程）：p246_ex8_25_experiment8_1_ADDER8B.TXT

-- VHDL code position: p246_ex8_25_experiment8_1_ADDER8B -- Note : This is code of multiplication by shifting -- See Also: example 8_24,8_25,8_26,8_27,8_28,8_29(top module) -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8B IS PORT ( CIN : IN STD_LOGIC; A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); COUT : OUT STD_LOGIC ); END ADDER8B; ARCHITECTURE struc OF ADDER8B IS SIGNAL SINT, AA, BB : STD_LOGIC_VECTOR( 8 DOWNTO 0 ); BEGIN AA <= '0' & A; BB <= '0' & B; SINT <= AA + BB + CIN; S <= SINT ( 7 DOWNTO 0 ); COUT <= SINT (8); END struc;