-- VHDL code position: p247_ex8_27_experiment8_1_REG16B -- Note : This is code of multiplication by shifting -- See Also: example 8_24,8_25,8_26,8_27,8_28,8_29(top module) -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG16B IS -- 16位锁存器 PORT ( CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END REG16B; ARCHITECTURE behav OF REG16B IS SIGNAL R16S : STD_LOGIC_VECTOR( 15 DOWNTO 0 ); BEGIN PROCESS( CLK, CLR ) BEGIN IF CLR = '1' THEN -- 清零信号 R16S <= "0000000000000000"; ELSIF CLK'EVENT AND CLK = '1' THEN -- 时钟到来时，锁存输入值，并右移低8位 R16S( 6 DOWNTO 0 ) <= R16S(7 DOWNTO 1); -- 右移低8位 R16S( 15 DOWNTO 7 ) <= D; -- 将输入锁到高8位 END IF; END PROCESS; Q <= R16S; END behav;