-- VHDL code position: p257_ex8_36_experiment8_3_sound
-- Note : This is code file of tennis play
-- See Also: example 8_35(top module), 8_36, 8_37, 8_38, 8_39, 8_40, 8_41, 8_42
-- Debug : no debug
---------------------------------------------------------------------------------
--球提示
library ieee;
use ieee.std_logic_1164.all;
entity sound is
port ( clk : in std_logic; --发声时钟
sig : in std_logic; --正确接球信号
en : in std_logic; --球拍接球脉冲
sout : out std_logic --提示声输出,接小喇叭
);
end entity sound;
architecture ful of sound is
begin
sout <= clk AND ( NOT sig ) AND en; --球拍接球,没接到时,发提示声
end architecture ful;