合肥工业大学：EDA技术与应用（精品课程）：p263_ex9_1_sequence_statement_case_mux41

-- VHDL code position: p263_ex9_1_sequence_statement_case_mux41 -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-1, 9_2, 9_3 -- Debug : no debug --------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity mux4 is port ( s1, s2, s3, s4 : in std_logic; z1, z2, z3, z4 : out std_logic ); end mux4 ; architecture activ of mux4 is SIGNAL sel : INTEGER RANGE 0 TO 15; BEGIN PROCESS ( sel, s1, s2, s3, s4 ) BEGIN sel <= '0'; IF( s1 = '1' ) THEN sel <= sel +1; ELSIF ( s2 = '1' ) THEN sel <= sel + 2; ELSIF ( s3 = '1' ) THEN sel <= sel + 2; ELSIF ( s2 = '1' ) THEN sel <= sel + 2; ELSE NULL; END IF; z1 <= '0'; z2 <= '0'; z3 <= '0'; z4 <= '0'; CASE sel IS WHEN 0 => z1 <= '1'; WHEN 1|3 => z2 <= '1'; WHEN 4 to 7|2 => z3 <= '1'; WHEN OTHERS => z4 <= '1'; END CASE; END PROCESS; end architecture activ ;