合肥工业大学：EDA技术与应用（精品课程）：p266_ex9_4_sequence_statement_loop_p_check

-- VHDL code position: p266_ex9_4_sequence_statement__loop_p_check -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-4, 9_5, -- Debug : no debug --------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- use ieee.std_logic_unsigned.all; entity p_check is port ( a : in std_logic_vector( 7 downto 0 ); y : out std_logic ); end p_check ; architecture behav of p_check is SIGNAL tmp : STD_LOGIC; BEGIN PROCESS ( a ) BEGIN tmp <= '0'; FOR n IN 0 TO 7 LOOP tmp <= tmp XOR a (n) END LOOP; y <= tmp; END PROCESS; end architecture behav ;