合肥工业大学：EDA技术与应用（精品课程）：p265_ex9_3_sequence_statement_case_alu

-- VHDL code position: p265_ex9_3_sequence_statement_case_alu.txt -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-1, 9_2, 9_3 -- Debug : no debug --------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alu is port ( a, b : in std_logic_vector( 7 downto 0 ); opcode : in std_logic_vector( 1 downto 0 ); result : out std_logic_vector( 7 downto 0 ) ); end alu ; architecture behav of alu is CONSTANT plus : std_logic_vector( 1 downto 0 ) := b"00"; CONSTANT minus : std_logic_vector( 1 downto 0 ) := b"01"; CONSTANT equal : std_logic_vector( 1 downto 0 ) := b"10"; CONSTANT not_equal : std_logic_vector( 1 downto 0 ) := b"11"; BEGIN PROCESS ( opcode, a, b ) BEGIN CASE opcode IS WHEN plus => result <= a + b; WHEN minus => result <= a - b; WHEN equal => IF ( a = b ) THEN result <= x"01"; ELSE result <= x"00"; END IF; WHEN not_equal => IF ( a /= b ) THEN result <= x"01"; ELSE result <= x"00"; END IF; END CASE; END PROCESS; end architecture behav ;