合肥工业大学：EDA技术与应用（精品课程）：p264_ex9_2_sequence_statement_case

-- VHDL code position: p264_ex9_2_sequence_statement_case -- Note : This is code for explaing sequence_statement of VHDL -- See Also: example 9-1, 9_2, 9_3 -- Debug : no debug --------------------------------------------------------------------------------- ...... SIGNAL valus : INTEGER RANGE 0 TO 15; SIGNAL out : STD_LOGIC; ...... -- error case code 1 CASE value IS END CASE; ...... -- error case code 2 CASE value IS WHEN 0 => out1 <= '1'; WHEN 1 => out2 <= '0'; END CASE; ...... -- error case code 3 CASE value IS WHEN 0 to 10 => out1 <= '1'; WHEN 5 to 15 => out2 <= '0'; END CASE; ......