-- VHDL code position: p246_ex8_24_experiment8_1_SREG8B -- Note : This is code of multiplication by shifting -- See Also: example 8_24,8_25,8_26,8_27,8_28,8_29(top module) -- Debug : no debug --------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SREG8B IS -- 8位右移寄存器 PORT ( CLK : IN STD_LOGIC; LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SREG8B; ARCHITECTURE behav OF SREG8B IS SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS (CLK, LOAD) BEGIN IF CLK'EVENT AND CLK = '1' THEN IF LOAD = '1' THEN -- 装载新数据 REG8 <= DIN; ELSE -- 数据右移 REG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1); END IF; END IF; END PROCESS; QB <= REG8(0); -- 输出最低位 END behav;