-- VHDL code position: p235_ex8_13_array_amp -- Note : This is code for explaining different data type convert of VHDL -- Debug : no debug --------------------------------------------------------------------------------- LIBARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY amp IS PORT ( a1, a2 : IN BIT_VECTOR ( 3 DOWNTO 0 ); c1, c2, c3 : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); b1, b2, b3 : INTEGER RANGE 0 TO 15; d1, d2, d3, d4 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ); END ENTITY amp ; ARCHITECTURE behav OF amp IS BEGIN d1 <= TO_STDLOGICVECTOR ( a1 AND a2 ); d2 <= CONV_STD_LOGIC_VECTOR ( b3, 4 ); d3 <= c1 WHEN conv_integer ( C2 ) = 8 else c3; d4 <= c1 WHEN c2 = 8 else c3; END ARCHITECTURE behav; --------------------------------------------------------- -- fellowing function is defined in IEEE.STD_LOGIC_UNSIGNED -- -- FUNCTION TO_SDLOGICVECTOR ( arg: BIT_VECTOR ) -- RETURN STD_LOGIC_VECTOR; -- -- FUNCTION CONV_INTEGER ( arg: STD_LOGIC_VECTOR ) -- RETURN INTEGER; -- -- FUNCTION CONV_STD_LOGIC_VECTOR ( arg: INTEGER ; size INTEGER ) -- RETURN STD_LOGIC_VECTOR; -- --