合肥工业大学：EDA技术与应用（精品课程）：p216_ex8_4_axamp

-- VHDL code position: p216_ex8_4_axamp -- Note : This is code for explaining "FUNCTION" statement -- Debug : no pass --------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE packexp IS FUNCTION max ( a, b : IN STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR; FUNCTION func1 ( a, b, c : REAL ) RETURN REAL; FUNCTION "*" ( a, b : IN STD_LOGIC_VECTOR ) RETURN INTEGER; FUNCTION as2 ( SIGNAL in1, in2 : REAL ) -- SIGNAL ?? RETURN STD_LOGIC_VECTOR; END; PACKAGE BODY packexp IS FUNCTION max ( a, b : IN STD_LOGIC_VECTOR ) RETURN STD_LOGIC_VECTOR IS BEGIN IF a > b THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION max; END BODY packexp ; ------------------------------------------------------------------- -- -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE WORK.packexp.all; ENTITY axamp IS PORT ( dat1, dat2 : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); dat3, dat4 : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ); out1, out2 : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ); END axamp; ARCHITECTURE behav OF axamp IS BEGIN out1 <= max (dat1, dat2); PROCESS ( dat2, dat4 ) BEGIN out2 <= max (dat3, dat4); END PROCESS; END ARCHITECTURE behav;