VHDL code position: p209_ex7_18_CNT9B
Note: 1: the top file see fig 7-34 of page 206,
2: sub-file also include example 7-17 of p208
2: The code is for simple oscillograph,
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CNT9B IS
PORT
(
CLK, CLR : IN STD_LOGIC;
FULL : OUT STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR( 8 DWONTO 0 )
);
END CNT9B;
ARCHITECTURE behav OF CNT9B IS
SIGNAL CQI : OUT STD_LOGIC_VECTOR( 8 DWONTO 0 );
BEGIN
PROCESS ( CLK )
BEGIN
IF CLR = '1' THEN
CQI <= "000000000";
ELSIF CLK'EVENT AND CLK = '1' THEN
CQI <= CQI + 1;
END IF;
END PROCESS;
PROCESS ( CQI )
BEGIN
IF CQI = "111111111" THEN
FULL <= '1';
ELSE
FULL <= '0';
END IF;
END PROCESS;
DOUT <= CQI;
END ARCHITECTURE behav;