合肥工业大学：EDA技术与应用（精品课程）：p194_ex7_11_RAM1.TXT

VHDL code position: p194_ex7_11_RAM1 Note: 1: The code is LPM_RAM code, 2: It be created by File -> MegaWizard Plug-In Manager of MAX+PLUS II ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY RAM1 IS PORT ( address : IN STD_LOGIC_VECTOR (8 DOWNTO 0); inclock : IN STD_LOGIC ; we : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END RAM1; ARCHITECTURE SYN OF RAM1 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_ram_dq GENERIC ( lpm_width : NATURAL; lpm_widthad : NATURAL; lpm_indata : STRING; lpm_address_control : STRING; lpm_outdata : STRING; lpm_hint : STRING ); PORT ( address : IN STD_LOGIC_VECTOR (8 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); we : IN STD_LOGIC ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); lpm_ram_dq_component : lpm_ram_dq GENERIC MAP ( LPM_WIDTH => 8, LPM_WIDTHAD => 9, LPM_INDATA => "REGISTERED", LPM_ADDRESS_CONTROL => "REGISTERED", LPM_OUTDATA => "UNREGISTERED", LPM_HINT => "USE_EAB=ON" ) PORT MAP ( address => address, inclock => inclock, data => data, we => we, q => sub_wire0 ); END ARCHITECTURE SYN;