VHDL code position: p202_ex7_16_SCHK Note: 1: The code is for sequence delete, 2: The code is also FSM code. ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY SCHK IS PORT ( DIN, CLK, CLR : IN STD_LOGIC; AB : OUT STD_LOGIC_VECTOR( 3 DWONTO 0 ) ); END SCHK; ARCHITECTURE behav OF SCHK IS SIGNAL Q : INTEGER RANGE 0 TO 8; SIGNAL D : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN D <= "11100101"; PROCESS ( CLK, CLR ) BEGIN IF CLR = '1' THEN Q <= 0; ELSIF CLK'EVENT AND CLK = '1' THEN CASE Q IS WHEN 0 => IF DIN = D ( 7 ) THEN Q <= 1; ELSE Q <= 0; END IF; WHEN 1 => IF DIN = D ( 6 ) THEN Q <= 2; ELSE Q <= 0; END IF; WHEN 2 => IF DIN = D ( 5 ) THEN Q <= 3; ELSE Q <= 0; END IF; WHEN 3 => IF DIN = D ( 4 ) THEN Q <= 4; ELSE Q <= 0; END IF; WHEN 4 => IF DIN = D ( 3 ) THEN Q <= 5; ELSE Q <= 0; END IF; WHEN 5 => IF DIN = D ( 2 ) THEN Q <= 6; ELSE Q <= 0; END IF; WHEN 6 => IF DIN = D ( 1 ) THEN Q <= 7; ELSE Q <= 0; END IF; WHEN 7 => IF DIN = D ( 0 ) THEN Q <= 8; ELSE Q <= 0; END IF; WHEN OTHERS => Q <= 0; END CASE; END IF; END PROCESS; PROCESS ( Q ) BEGIN IF Q = 8 THEN AB <= "1010"; ELSE AB <= "1011"; END IF; END PROCESS; END ARCHITECTURE behav;